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| 74AUP1G885 Low-power dual function gate Rev. 01.00 -- 26 January 2006 Preliminary data sheet 1. General description The 74AUP1G885 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74AUP1G885 provides two functions in one device.The output state of the outputs (1Y, 2Y) is determined by the inputs (A, B and C). The output 1Y provides the boolean funtion: 1Y = A x C. The output 2Y provides the boolean funtion: 2Y = A x B + A x C 2. Features s Wide supply voltage range from 0.8 V to 3.6 V s High noise immunity s Complies with JEDEC standards: x JESD8-12 (0.8 V to 1.3 V) x JESD8-11 (0.9 V to 1.65 V) x JESD8-7 (1.2 V to 1.95 V) x JESD8-5 (1.8 V to 2.7 V) x JESD8-B (2.7 V to 3.6 V) s ESD protection: x HBM JESD22-A114-C Class 3A exceeds 4000 V x MM JESD22-A115-A exceeds 200 V x CDM JESD22-C101-C exceeds 1000 V s Low static power consumption; ICC = 0.9 A (maximum) s Latch-up performance exceeds 100 mA per JESD 78 Class II s Inputs accept voltages up to 3.6 V s Low noise overshoot and undershoot < 10 % of VCC s IOFF circuitry provides partial Power-down mode operation s Multiple package options s Specified from -40 C to +85 C and -40 C to +125 C Philips Semiconductors 74AUP1G885 Low-power dual function gate 3. Quick reference data Table 1: Quick reference data GND = 0 V; Tamb = 25 C; tr = tf 3 ns. Symbol Parameter Conditions CL = 5 pF; RL = 1 M; VCC = 0.8 V CL = 5 pF; RL = 1 M; VCC = 1.1 V to 1.3 V CL = 5 pF; RL = 1 M; VCC = 1.4 V to 1.6 V CL = 5 pF; RL = 1 M; VCC = 1.65 V to 1.95 V CL = 5 pF; RL = 1 M; VCC = 2.3 V to 2.7 V CL = 5 pF; RL = 1 M; VCC = 3.0 V to 3.6 V tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay A, B to 2Y CL = 5 pF; RL = 1 M; VCC = 0.8 V CL = 5 pF; RL = 1 M; VCC = 1.1 V to 1.3 V CL = 5 pF; RL = 1 M; VCC = 1.4 V to 1.6 V CL = 5 pF; RL = 1 M; VCC = 1.65 V to 1.95 V CL = 5 pF; RL = 1 M; VCC = 2.3 V to 2.7 V CL = 5 pF; RL = 1 M; VCC = 3.0 V to 3.6 V CI CPD input capacitance power dissipation capacitance VCC = 1.8 V; f = 1 MHz VCC = 3.3 V; f = 1 MHz [1] [2] [1] [2] Min 1.1 1.2 1.1 1.1 1.1 1.7 1.7 1.4 1.2 1.1 - Typ 17.3 5.2 3.7 3.0 2.4 2.1 21.5 6.0 4.2 3.3 2.6 2.3 0.8 3.1 4.1 Max 9.7 5.9 4.8 3.6 3.1 12.7 7.2 5.8 4.1 3.5 - Unit ns ns ns ns ns ns ns ns ns ns ns ns pF pF pF tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay A, C to 1Y [1] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL x VCC2 x fo) = sum of the outputs. The condition is VI = GND to VCC. [2] 74AUP1G885_1 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.00 -- 26 January 2006 2 of 19 Philips Semiconductors 74AUP1G885 Low-power dual function gate 4. Ordering information Table 2: Ordering information Package Temperature range Name 74AUP1G885DC 74AUP1G885GT -40 C to +125 C -40 C to +125 C VSSOP8 XSON8 Description Version plastic very thin shrink small outline package; 8 leads; SOT765-1 body width 2.3 mm plastic extremely thin small outline package; no leads; SOT833-1 8 terminals; body 1 x 1.95 x 0.5 mm Type number 5. Marking Table 3: Marking Marking code pS8 pS8 Type number 74AUP1G885DC 74AUP1G885GT 6. Functional diagram 1 3 B 2 A 2Y C 6 7 1Y 001aae353 Fig 1. Logic diagram 74AUP1G885_1 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.00 -- 26 January 2006 3 of 19 Philips Semiconductors 74AUP1G885 Low-power dual function gate 7. Pinning information 7.1 Pinning 74AUP1G885 A 1 8 VCC B 2 7 1Y 74AUP1G885 2Y A B 2Y GND 1 2 3 4 001aae354 3 6 C 8 7 6 5 VCC 1Y C n.c. GND 4 5 n.c. 001aae355 Transparent top view Fig 2. Pin configuration SOT765-1 (VSSOP8) Fig 3. Pin configuration SOT833-1 (XSON8) 7.2 Pin description Table 4: Symbol A B 2Y GND n.c. C 1Y VCC Pin description Pin 1 2 3 4 5 6 7 8 Description data input A data input B data output 2Y ground (0 V) not connected data input C data output 1Y supply voltage 74AUP1G885_1 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.00 -- 26 January 2006 4 of 19 Philips Semiconductors 74AUP1G885 Low-power dual function gate 8. Functional description 8.1 Function table Table 5: Input A L H L H L H L H [1] Function table [1] Output B L L H H L L H H C L L L L H H H H 1Y L L L L L H L H 2Y L H H H L L H L H = HIGH voltage level; L = LOW voltage level. 9. Limiting values Table 6: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK VI IOK VO IO ICC IGND Tstg Ptot [1] [2] Parameter supply voltage input clamping current input voltage output clamping current output voltage output current quiescent supply current ground current storage temperature total power dissipation Conditions VI < 0 V [1] Min -0.5 -0.5 [1] [1] Max +4.6 -50 +4.6 -50 Unit V mA V mA VO < 0 V active mode Power-down mode VO = 0 V to VCC -0.5 -0.5 -65 VCC + 0.5 V +4.6 20 +50 -50 +150 300 V mA mA mA C mW Tamb = -40 C to +125 C [2] - The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed. For VSSOP8 packages: above 110 C the value of Ptot derates linearly with 8.0 mW/K. For XSON8 packages: above 45 C the value of Ptot derates linearly with 2.4 mW/K. 74AUP1G885_1 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.00 -- 26 January 2006 5 of 19 Philips Semiconductors 74AUP1G885 Low-power dual function gate 10. Recommended operating conditions Table 7: Symbol VCC VI VO Tamb t/V Recommended operating conditions Parameter supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 0.8 V to 3.6 V active mode Power-down mode; VCC = 0 V Conditions Min 0.8 0 0 0 -40 0 Max 3.6 3.6 VCC 3.6 +125 200 Unit V V V V C ns/V 11. Static characteristics Table 8: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = 25 C VIH HIGH-state input voltage VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VIL LOW-state input voltage VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VOH HIGH-state output voltage VI = VIH or VIL IO = -20 A; VCC = 0.8 V to 3.6 V IO = -1.1 mA; VCC = 1.1 V IO = -1.7 mA; VCC = 1.4 V IO = -1.9 mA; VCC = 1.65 V IO = -2.3 mA; VCC = 2.3 V IO = -3.1 mA; VCC = 2.3 V IO = -2.7 mA; VCC = 3.0 V IO = -4.0 mA; VCC = 3.0 V VCC - 0.1 1.11 1.32 2.05 1.9 2.72 2.6 V V V V V V V V 0.75 x VCC 0.70 x VCC 0.65 x VCC 1.6 2.0 V V V V Conditions Min Typ Max Unit 0.30 x VCC V 0.35 x VCC V 0.7 0.9 V V 74AUP1G885_1 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.00 -- 26 January 2006 6 of 19 Philips Semiconductors 74AUP1G885 Low-power dual function gate Table 8: Static characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VOL LOW-state output voltage Conditions VI = VIH or VIL IO = 20 A; VCC = 0.8 V to 3.6 V IO = 1.1 mA; VCC = 1.1 V IO = 1.7 mA; VCC = 1.4 V IO = 1.9 mA; VCC = 1.65 V IO = 2.3 mA; VCC = 2.3 V IO = 3.1 mA; VCC = 2.3 V IO = 2.7 mA; VCC = 3.0 V IO = 4.0 mA; VCC = 3.0 V II IOFF IOFF ICC ICC CI CO VIH input leakage current power-off leakage current additional power-off leakage current quiescent supply current VI = GND to 3.6 V; VCC = 0 V to 3.6 V VI or VO = 0 V to 3.6 V; VCC = 0 V VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V [1] Min - Typ 0.8 1.7 Max 0.1 0.3 x VCC 0.31 0.31 0.31 0.44 0.31 0.44 0.1 0.2 0.2 0.5 40 - Unit V V V V V V V V A A A A A pF pF V V V V additional quiescent supply VI = VCC - 0.6 V; IO = 0 A; current VCC = 3.3 V input capacitance output capacitance HIGH-state input voltage VCC = 0 V to 3.6 V; VI = GND or VCC VO = GND; VCC = 0 V VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V Tamb = -40 C to +85 C 0.70 x VCC 0.65 x VCC 1.6 2.0 VCC - 0.1 0.7 x VCC 1.03 1.30 1.97 1.85 2.67 2.55 - VIL LOW-state input voltage VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V 0.30 x VCC V 0.35 x VCC V 0.7 0.9 V V V V V V V V V V VOH HIGH-state output voltage VI = VIH or VIL IO = -20 A; VCC = 0.8 V to 3.6 V IO = -1.1 mA; VCC = 1.1 V IO = -1.7 mA; VCC = 1.4 V IO = -1.9 mA; VCC = 1.65 V IO = -2.3 mA; VCC = 2.3 V IO = -3.1 mA; VCC = 2.3 V IO = -2.7 mA; VCC = 3.0 V IO = -4.0 mA; VCC = 3.0 V 74AUP1G885_1 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.00 -- 26 January 2006 7 of 19 Philips Semiconductors 74AUP1G885 Low-power dual function gate Table 8: Static characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VOL LOW-state output voltage Conditions VI = VIH or VIL IO = 20 A; VCC = 0.8 V to 3.6 V IO = 1.1 mA; VCC = 1.1 V IO = 1.7 mA; VCC = 1.4 V IO = 1.9 mA; VCC = 1.65 V IO = 2.3 mA; VCC = 2.3 V IO = 3.1 mA; VCC = 2.3 V IO = 2.7 mA; VCC = 3.0 V IO = 4.0 mA; VCC = 3.0 V II IOFF IOFF ICC ICC input leakage current power-off leakage current additional power-off leakage current quiescent supply current VI = GND to 3.6 V; VCC = 0 V to 3.6 V VI or VO = 0 V to 3.6 V; VCC = 0 V VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V [1] Min - Typ - Max 0.1 0.3 x VCC 0.37 0.35 0.33 0.45 0.33 0.45 0.5 0.5 0.6 0.9 50 Unit V V V V V V V V A A A A A additional quiescent supply VI = VCC - 0.6 V; IO = 0 A; current VCC = 3.3 V HIGH-state input voltage VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V Tamb = -40 C to +125 C VIH 0.75 x VCC 0.70 x VCC 1.6 2.0 V V V V VIL LOW-state input voltage VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V 0.25 x VCC V 0.30 x VCC V 0.7 0.9 V V V V V V V V V V VOH HIGH-state output voltage VI = VIH or VIL IO = -20 A; VCC = 0.8 V to 3.6 V IO = -1.1 mA; VCC = 1.1 V IO = -1.7 mA; VCC = 1.4 V IO = -1.9 mA; VCC = 1.65 V IO = -2.3 mA; VCC = 2.3 V IO = -3.1 mA; VCC = 2.3 V IO = -2.7 mA; VCC = 3.0 V IO = -4.0 mA; VCC = 3.0 V VCC - 0.11 0.6 x VCC 0.93 1.17 1.77 1.67 2.40 2.30 - 74AUP1G885_1 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.00 -- 26 January 2006 8 of 19 Philips Semiconductors 74AUP1G885 Low-power dual function gate Table 8: Static characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VOL LOW-state output voltage Conditions VI = VIH or VIL IO = 20 A; VCC = 0.8 V to 3.6 V IO = 1.1 mA; VCC = 1.1 V IO = 1.7 mA; VCC = 1.4 V IO = 1.9 mA; VCC = 1.65 V IO = 2.3 mA; VCC = 2.3 V IO = 3.1 mA; VCC = 2.3 V IO = 2.7 mA; VCC = 3.0 V IO = 4.0 mA; VCC = 3.0 V II IOFF IOFF ICC ICC input leakage current power-off leakage current additional power-off leakage current quiescent supply current VI = GND to 3.6 V; VCC = 0 V to 3.6 V VI or VO = 0 V to 3.6 V; VCC = 0 V VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V [1] Min - Typ - Max 0.11 0.41 0.39 0.36 0.50 0.36 0.50 0.75 0.75 0.75 1.4 75 Unit V V V V V V V A A A A A 0.33 x VCC V additional quiescent supply VI = VCC - 0.6 V; IO = 0 A; current VCC = 3.3 V [1] One input at VCC - 0.6 V, other input at VCC or GND. 12. Dynamic characteristics Table 9: Dynamic characteristics Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 5 Symbol tPHL, tPLH Parameter HIGH-to-LOW and LOW-to-HIGH propagation delay A, C to 1Y Conditions see Figure 4 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay A, B to 2Y see Figure 4 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V 1.7 1.7 1.4 1.2 1.1 21.5 6.0 4.2 3.3 2.6 2.3 12.7 7.2 5.8 4.1 3.5 ns ns ns ns ns ns 1.1 1.2 1.1 1.1 1.1 17.3 5.2 3.7 3.0 2.4 2.1 9.7 5.9 4.8 3.6 3.1 ns ns ns ns ns ns Min Typ [1] Max Unit Tamb = 25 C; CL = 5 pF 74AUP1G885_1 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.00 -- 26 January 2006 9 of 19 Philips Semiconductors 74AUP1G885 Low-power dual function gate Table 9: Dynamic characteristics ...continued Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 5 Symbol tPHL, tPLH Parameter HIGH-to-LOW and LOW-to-HIGH propagation delay A, C to 1Y Conditions see Figure 4 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay A, B to 2Y see Figure 4 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V Tamb = 25 C; CL = 15 pF tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay A, C to 1Y see Figure 4 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay A, B to 2Y see Figure 4 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V Tamb = 25 C; CL = 30 pF tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay A, C to 1Y see Figure 4 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V 2.4 2.5 2.5 2.6 2.5 34.7 9.2 6.5 5.4 4.5 4.2 17.7 10.6 8.5 6.4 5.7 ns ns ns ns ns ns 2.1 2.2 2.0 1.8 1.7 28.5 7.7 5.4 4.4 3.6 3.3 16.0 9.4 7.4 5.5 4.8 ns ns ns ns ns ns 1.3 1.7 1.5 1.7 1.7 24.3 6.9 4.9 4.1 3.4 3.1 13.0 8.0 6.4 5.0 4.4 ns ns ns ns ns ns 1.8 1.9 1.9 1.5 1.4 25.0 6.9 4.8 3.9 3.1 2.8 14.4 8.5 6.6 4.7 4.3 ns ns ns ns ns ns 1.2 1.4 1.4 1.4 1.4 20.8 6.1 4.3 3.6 2.9 2.7 11.4 7.2 5.7 4.2 3.9 ns ns ns ns ns ns Min Typ [1] Max Unit Tamb = 25 C; CL = 10 pF 74AUP1G885_1 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.00 -- 26 January 2006 10 of 19 Philips Semiconductors 74AUP1G885 Low-power dual function gate Table 9: Dynamic characteristics ...continued Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 5 Symbol tPHL, tPLH Parameter HIGH-to-LOW and LOW-to-HIGH propagation delay A, B to 2Y Conditions see Figure 4 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V Tamb = 25 C CPD power dissipation capacitance f = 1 MHz VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V [1] [2] All typical values are measured at nominal VCC. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL x VCC2 x fo) = sum of the outputs. The condition is VI = GND to VCC. [2] [3] Min 2.6 2.6 2.7 2.5 2.4 Typ 38.9 10.0 6.9 5.7 4.7 4.4 [1] Max 20.5 11.9 9.5 6.9 6.1 Unit ns ns ns ns ns ns - 2.7 2.9 3.0 3.1 3.5 4.1 - pF pF pF pF pF pF [3] 74AUP1G885_1 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.00 -- 26 January 2006 11 of 19 Philips Semiconductors 74AUP1G885 Low-power dual function gate Table 10: Dynamic characteristics Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 5 Symbol CL = 5 pF tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay A, C to 1Y see Figure 4 VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay A, B to 2Y see Figure 4 VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V CL = 10 pF tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay A, C to 1Y see Figure 4 VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay A, B to 2Y see Figure 4 VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V CL = 15 pF tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay A, C to 1Y see Figure 4 VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay A, B to 2Y see Figure 4 VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V 74AUP1G885_1 Parameter Conditions -40 C to +85 C Min Max -40 C to +125 C Min Max Unit 0.9 1.0 0.9 1.0 1.0 1.4 1.4 1.2 1.0 0.9 12.8 7.8 6.2 4.1 3.6 12.8 7.8 6.5 4.7 3.8 0.9 1.0 0.9 1.0 1.0 1.4 1.4 1.2 1.0 0.9 14.2 8.6 6.9 4.5 4.1 14.2 8.7 7.2 5.2 4.2 ns ns ns ns ns ns ns ns ns ns 1.2 1.2 1.3 1.2 1.3 1.7 1.5 1.7 1.3 1.3 14.6 8.7 6.8 4.8 4.1 14.6 9.1 7.2 5.4 4.6 1.2 1.2 1.3 1.2 1.3 1.7 1.5 1.7 1.3 1.3 16.1 9.6 7.5 5.4 4.6 16.1 10.1 8.0 5.9 5.1 ns ns ns ns ns ns ns ns ns ns 1.2 1.4 1.4 1.6 1.6 1.9 2.4 1.8 1.6 1.5 16.2 9.7 7.6 5.4 4.7 16.3 10.3 8.2 6.0 5.2 1.2 1.4 1.4 1.6 1.6 1.9 2.4 1.8 1.6 1.5 17.9 10.8 8.4 6.0 5.3 18.0 11.4 9.1 6.7 5.8 ns ns ns ns ns ns ns ns ns ns (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.00 -- 26 January 2006 12 of 19 Philips Semiconductors 74AUP1G885 Low-power dual function gate Table 10: Dynamic characteristics ...continued Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 5 Symbol CL = 30 pF tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay A, C to 1Y see Figure 4 VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay A, B to 2Y see Figure 4 VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V 2.6 2.6 2.7 2.5 2.4 21.5 13.2 10.5 7.6 7.1 2.6 2.6 2.7 2.5 2.4 23.7 14.5 11.6 8.4 7.9 ns ns ns ns ns 2.3 2.5 2.4 2.4 2.3 20.9 12.2 9.4 7.0 6.6 2.3 2.5 2.4 2.4 2.3 23.0 13.5 10.4 7.7 7.3 ns ns ns ns ns Parameter Conditions -40 C to +85 C Min Max -40 C to +125 C Min Max Unit 13. Waveforms VI A, B, C input GND t PHL VOH nY output VOL VM 001aae356 VM t PLH Measurement points are given in Table 11. Logic levels: VOL and VOH are typical output voltage drop that occur with the output load. Fig 4. The data input (A, B, C) to output (nY) propagation delays Table 11: VCC 0.8 V to 3.6 V Measurement points Output VM 0.5 x VCC Input VM 0.5 x VCC VI VCC tr = tf 3.0 ns Supply voltage 74AUP1G885_1 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.00 -- 26 January 2006 13 of 19 Philips Semiconductors 74AUP1G885 Low-power dual function gate VCC VEXT 5 k PULSE GENERATOR VI VO DUT RT CL RL 001aac521 Test data is given in Table 12. Definitions for test circuit: RL = Load resistance CL = Load capacitance including jig and probe capacitance RT = Termination resistance should be equal to the output impedance Zo of the pulse generator VEXT = External voltage for measuring switching times. Fig 5. Load circuitry for switching times Table 12: VCC 0.8 V to 3.6 V [1] Test data Load CL RL [1] Supply voltage VEXT tPLH, tPHL tPZH, tPHZ GND tPZL, tPLZ 2 x VCC 5 pF, 10 pF, 5 k or 1 M open 15 pF and 30 pF For measuring enable and disable times RL = 5 k, for measuring propagation delays, setup and hold times and pulse width RL = 1 M. 74AUP1G885_1 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.00 -- 26 January 2006 14 of 19 Philips Semiconductors 74AUP1G885 Low-power dual function gate 14. Package outline VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 D E A X c y HE vMA Z 8 5 Q A pin 1 index A2 A1 (A3) Lp L 1 e bp 4 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1 A1 0.15 0.00 A2 0.85 0.60 A3 0.12 bp 0.27 0.17 c 0.23 0.08 D(1) 2.1 1.9 E(2) 2.4 2.2 e 0.5 HE 3.2 3.0 L 0.4 Lp 0.40 0.15 Q 0.21 0.19 v 0.2 w 0.13 y 0.1 Z(1) 0.4 0.1 8 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 REFERENCES IEC JEDEC MO-187 JEITA EUROPEAN PROJECTION ISSUE DATE 02-06-07 Fig 6. Package outline SOT765-1 (VSSOP8) 74AUP1G885_1 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.00 -- 26 January 2006 15 of 19 Philips Semiconductors 74AUP1G885 Low-power dual function gate XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm SOT833-1 1 2 3 b 4 4x L (2) L1 e 8 e1 7 e1 6 e1 5 8x (2) A A1 D E terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) UNIT mm A (1) max 0.5 A1 max 0.04 b 0.25 0.17 D 2.0 1.9 E 1.05 0.95 e 0.6 e1 0.5 L 0.35 0.27 L1 0.40 0.32 1 scale 2 mm Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT833-1 REFERENCES IEC --JEDEC MO-252 JEITA --EUROPEAN PROJECTION ISSUE DATE 04-07-22 04-11-09 Fig 7. Package outline SOT833-1 (XSON8) 74AUP1G885_1 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.00 -- 26 January 2006 16 of 19 Philips Semiconductors 74AUP1G885 Low-power dual function gate 15. Abbreviations Table 13: Acronym CDM CMOS DUT ESD HBM MM TTL Abbreviations Description Charged Device Model Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor Transistor Logic 16. Revision history Table 14: Revision history Release date 74AUP1G885_1 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.00 -- 26 January 2006 17 of 19 Philips Semiconductors 74AUP1G885 Low-power dual function gate 17. Data sheet status Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). III Product data Production [1] [2] [3] Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 18. Definitions Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 20. Trademarks Notice -- All referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Disclaimers Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors 21. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com 74AUP1G885_1 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.00 -- 26 January 2006 18 of 19 Philips Semiconductors 74AUP1G885 Low-power dual function gate 22. Contents 1 2 3 4 5 6 7 7.1 7.2 8 8.1 9 10 11 12 13 14 15 16 17 18 19 20 21 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information . . . . . . . . . . . . . . . . . . . . 18 (c) Koninklijke Philips Electronics N.V. 2006 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 26 January 2006 Document number: 74AUP1G885_1 Published in The Netherlands |
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